With the scaling of integrated circuits, applications require an increasingly faster speed. This puts a requirement on the metal-oxide-semiconductor (MOS) devices, demanding that the MOS devices switch faster. As is known in the art, to increase the speed of MOS devices, high dielectric constant values (k values) of the gate dielectrics are desired. Since conventional silicon oxide, which has a k value of about 3.9, cannot satisfy such a requirement, high-k dielectric materials, which include oxides, nitrides, and oxynitrides, are increasingly used.
Such a MOS device 100 is illustrated in FIG. 1, which has a substrate 101 with isolation regions 103, a gate dielectric 105, a gate electrode 107, source/drain regions 109, and spacers 111. In this device 100 the gate dielectric 105 is formed from a high-k dielectric material in order to increase the switching speed of the device.
However, when the gate electrode 107 is formed directly over the high-k material in the gate dielectric 105, an effect known as Fermi-level pinning occurs which can reduce the switching speed of the device 100. This “pinning” of the Fermi layer along the interface of the gate dielectric 105 and the gate electrode 107 is the result of two causes. The first cause is dangling bonds (broken covalent bonds) along the edge of the high-k material that will bond with the deposited gate electrode and form a “pinned” interface state. The second cause is a lack of oxygen bonds along the interface and the high-k material. Both of these causes have an effect on the Fermi-level pinning of the interface, thereby decreasing the efficiency of the device as a whole.
Accordingly, what is needed is a device and method of formation to either reduce the dangling bonds of the high-k material or increase the amount of oxygen along the interface.